Embedded DSP Processor Design: Application Specific Instruction Set ProcessorsElsevier, 9 lug 2008 - 808 pagine This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers. Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples.
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Sommario
| 1 | |
| 47 | |
Chapter 3 DSP Architectures | 87 |
Chapter 4 DSP ASIP Design Flow | 159 |
Chapter 5 A Simple DSP CoreThe Junior Processor | 187 |
Chapter 6 Code Profiling for ASIP Design | 217 |
Chapter 7 Assembly Instruction Set Design | 239 |
Chapter 8 Software Development Toolchain | 315 |
Chapter 13 MAC Hardware Implementation | 439 |
Chapter 14 Control Path Design | 475 |
Chapter 15 Design of Memory Subsystems | 513 |
Chapter 16 DSP Core Peripherals | 547 |
Chapter 17 Design for DSP Functional Acceleration | 597 |
Chapter 18 Realtime Fixedpoint DSP Firmware | 619 |
Chapter 19 ASIP Integration and Verification | 663 |
Chapter 20 Parallel Streaming Signal Processing | 705 |
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Embedded DSP Processor Design: Application Specific Instruction Set Processors Dake Liu Anteprima limitata - 2008 |
Parole e frasi comuni
accelerator accumulator register algorithms architecture arithmetic ASIP design assembly code assembly instruction set assembly language baseband behavior benchmarking buffer cache circuit CISC clock cycles compiler complexity computing configuration control path control signals convolution cycle cost data block data memory datapath DMA controller DMA transaction DSP core DSP processor DSP subsystem dynamic range embedded system example execution fetched FIFO Figure filter firmware fixed-point flag floating-point full adder functions guard bits hardware module implemented input instruction decoder instruction set simulator integration interface interrupt interrupt request iterative jump kernel load logic loop machine main memory memory access memory addressing microarchitecture microoperations multiple on-chip operand operations output parallel partitioned performance peripheral module pipeline port processor core program memory real-time register file result RISC RTL code running runtime saturation signal processing silicon cost SIMD source code specification stored subroutine superscalar Table task vector verification VLIW