The 68000 Microprocessor Family: Architecture, Programming, and Applications

ACIA address bus address lines address mode address register BERR Bit Bit Bit BRA.S buffers bus cycle bus error byte chip select circuit clock command Condition Codes contents control register coprocessor Courtesy of Motorola data bus data cache data register data transfer decoder decremented descriptor destination device display DTACK effective address Enable EPROM example exception routine execution fetched Figure flag floating point index register indicates initially input interface interrupt mask interrupt request keyboard loaded location $00 logical address long word lower word memory location memory management unit microprocessor Motorola MOVE.W occurs operand operation output parity peripheral pins port processor program counter pulse Receive Data reset otherwise result sign extended signal stack pointer status register stored subroutine subtraction supervisor Table timer translation transmit vector virtual memory voltage Write zero